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Summary

• Capture 50MHz+ waveforms on 32 channels
  • 200Msps captures up to 100MHz waveforms on 16 channels
  • 100Msps captures up to 50MHz waveforms on 32 channels
• 16 buffered channels, 5volt tolerant
  • M74LCX16245DTR2G transceiver tolerates voltages from -0.5V to +7V.
• 216K Block RAM supports following memory configurations*
  • 8 channels with 24K sample depth
  • 16 channels with 12K sample depth
  • 32 channels with 6K sample depth
• External clock and trigger input
  • Allows interfacing with external test equipment and daisy chaining OLS's for additional channels.
• Internal clock and trigger output
• 16bit wing expansion header
• USB interface, USB powered
• Designed for the SUMP logic analyzer client
• Open source
• Low price

Hardware Subsections

USB

The FPGA only communicates over a serial port, so we used a USB microcontroller to convert the serial IO to a USB virtual serial port. The entire chain is upgradable through the USB connection. The microcontroller can program updated logic analyzer designs into the SPI flash data chip, and the microcontroller can also be updated from its USB bootloader.

We chose a USB microcontroller over a dedicated USB interface chip. A low pincount PIC was cheaper than most other USB bridge options. It’s USB 2.0 compliant, and can transfer data at up to 12Mbps. We’re using it with the completely open virtual serial port CDC interface, so it will work on almost any platform without proprietary drivers. The PIC can also implement other USB transfer protocols with a firmware update, faster connection methods can be supported when someone adds support for them to the SUMP client software.

Power supply

The board is intended to be powered by the 5volt supply from a USB port. Three regulators provide the three supply rails required by the circuit. All the chips require a 3.3volt supply (VR1), the FPGA also requires a 1.2volt (VR3) and 2.5volt (VR2) supply. As recommended by the datasheet, there’s a 10uF capacitor (C27) on the supply line, and each regulator has a 1.0uF capacitor (C1-3) on the output pin.

PIC Microcontroller

The ROM chip has an SPI interface that connects to the FPGA, the PIC microcontroller, and an external programming header.

• The FPGA mode select pin configuration causes the FPGA to load a bitstream from the ROM chip. When the bitstream is finished loading, the DONE signal goes high, and the FPGA is programmed and active.
• The PIC can (re)program the ROM with updated bitstreams. The PIC holds the FPGA PROG_B line low in this mode so the FPGA releases control of the ROM chip.
• The external header can be used to program the ROM from a programmer. Place a jumper between the PGM and EN pins to manually place the FPGA in programming mode.

Microcontroller

A PIC 18F24J50 microcontroller (IC1) is the interface glue. It has these functions:

• Provides a USB->serial connection from the SUMP Java client to the SUMP hardware in the FPGA
• Puts the FPGA in programming mode and updates the ROM with a new bitstream
• A USB bootloader can be used to update the PIC firmware

Xilinx FPGA

FPGA

A Xilinx Spartan 3E field programmable gate array (FPGA) is the central component of the logic analyzer. The FPGA samples data from 16 buffered and 16 unbuffered IO pins, and stores the samples in internal RAM. The samples are later dumped out a serial UART to the PIC, and from the PIC to a computer via USB.

The FPGA (IC3) requires three different power supplies. The core requires 1.2volts and 2.5volts, and the IO pins run at 3.3volts. Each supply pin gets a 0.1uF decoupling capacitor (C11-26). We brought the JTAG programming and debugging connection to a header in the interior of the PCB. The JTAG header provides 2.5V to external JTAG programmers to satisfy the Spartan 3E’s requirements for 2.5V on the dedicated JTAG pins.

5V Tolerant Header

We also brought the one of the hardware UARTs to a header. The pins are 5volt tolerant, and can be interfaced at up to 5volts without damaging the PIC. This header can be used for a ‘classic’ serial port connection. The board can also be powered through the UART header supply pins.

Wing Header

Wing Header

A wing is an accessory for the Gadget Factory Butterfly Platform development board. It uses a standardized header and pinout. The header has 16bits of 3.3volt IO, and 2.5, 3.3, and 5volt power supplies.

We added a wing header to the OLS so it can use accessories developed on the Butterfly Platform, like a digital sampling oscilloscope. This has the added benefit of making the OLS compatible with a bunch of existing Butterfly Platform accessories.

ROM

ROM

The FPGA programs itself with a bitstream stored in a 4Mbit AT45DB041D SPI flash storage chip (IC2), we refer to it as a ROM. We previously demonstrated this chip with the Bus Pirate. It’s powered by the 3.3volt supply, and requires a 0.1uF capacitor (C10) on the supply pin. The XC3S250E bitstream will fit into a 2Mbit flash chip, but only 4Mbit chips were available when we sourced parts.

The ROM chip has an SPI interface that connects to the FPGA, the PIC microcontroller, and an external programming header.

• The FPGA mode select pin configuration causes the FPGA to load a bitstream from the ROM chip. When the bitstream is finished loading, the DONE signal goes high, and the FPGA is programmed and active.
• The PIC can (re)program the ROM with updated bitstreams. The PIC holds the FPGA PROG_B line low in this mode so the FPGA releases control of the ROM chip.
• The external header can be used to program the ROM from a programmer. Place a jumper between the PGM and EN pins to manually place the FPGA in programming mode.

Clock/trigger headers

Clock/trigger headers

The logic analyzer can sync with other test equipment and should allow OLS’s to be daisy chained together for more channels. It can be driven by an external clock and trigger, and it also outputs its internal clock and trigger. You can tap these signals from the some-what awkwardly placed pin block in the middle of the PCB. The external clock input had to be on an FPGA global clock pin, this was the best possible location to access it because no sensitive high-speed signals were routed across other traces.